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Search Jobs Find Jobs For Where? Search Jobs ASIC Physical Design, Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 04/07/2026 Category Engineering Hire Type Employee Job ID 16700 Remote Eligible No Date Posted 04/07/2026 We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are:You are a passionate and highly-skilled engineer eager to make a tangible impact in the world of semiconductor innovation. Your strong technical foundation in ASIC physical design is complemented by a collaborative mindset and an eagerness to solve complex challenges. You thrive in a dynamic, multicultural environment, seamlessly engaging with both local and international colleagues. Your attention to detail and perseverance shine through when tackling tight timing closures and integrating mixed-signal macro IPs. You possess a deep understanding of advanced technology nodes, including 10nm, 7nm, 6nm, and below, and are excited to work on world-class DDR IP implementation. You are a proactive communicator, adept at translating technical concepts into actionable solutions, and you excel in balancing rigorous technical requirements with practical design constraints. As a continuous learner, you stay updated on emerging industry trends and best practices, and your integrity and reliability make you a trusted member of the team. If you’re ready to push the boundaries of silicon design and collaborate with some of the brightest minds in the industry, Synopsys is your ideal next step.What You’ll Be Doing:Implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).Performing timing closure for designs operating above ~4GHz, ensuring robust performance and reliability.Collaborating daily with local and US counterparts to align on technical challenges and project milestones.Integrating mixed-signal macro IPs and optimizing their placement within complex chip architectures.Designing and building efficient clock trees with exceptionally tight skew balancing to meet stringent requirements.Driving continuous improvement in implementation methodologies and sharing best practices across the team.Participating in design reviews, providing critical feedback and innovative solutions to enhance project outcomes.The Impact You Will Have:Enabling high-performance DDR IP integration, which powers next-generation computing, networking, and storage solutions.Accelerating the delivery of silicon chips at cutting-edge technology nodes, advancing Synopsys’ leadership in the industry.Strengthening Synopsys’ reputation for innovation and reliability through your technical expertise and dedication.Contributing to successful project execution by bridging technical knowledge between global teams.Driving quality improvements and efficiency in physical design processes, setting new standards for excellence.Mentoring and guiding junior engineers, helping build a stronger, more resilient team.What You’ll Need:Strong technical concepts with 3+yrs in ASIC physical design.Hands-on experience with DDR IP implementation and timing closure, especially at advanced nodes (10nm, 7nm, 6nm and below).Proficiency in EDA tools for synthesis, place-and-route, and timing analysis.Expertise in clock tree synthesis and balancing skew within tight constraints.Experience integrating mixed-signal macro IPs into complex SoC designs.Ability to work collaboratively with cross-cultural and cross-functional teams, including US counterparts.Who You Are:Detail-oriented and analytical, with a drive for technical excellence.Effective communicator, capable of explaining complex concepts clearly.Adaptable and resilient in fast-paced, dynamic environments.Collaborative team player, open to feedback and eager to share knowledge.Proactive problem solver who thrives on tackling new challenges.Committed to continuous learning and professional growth.The Team You’ll Be A Part Of:You'll join the SNPS DDR IP implementation team—a diverse, innovative group focused on delivering world-class DDR IP solutions at the forefront of technology. The team values collaboration, knowledge-sharing, and a commitment to excellence, working closely with both local and US counterparts to achieve remarkable results in silicon design and integration.Rewards and Benefits:We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. let elementId = "chq_1733352155806"; let scriptURL = "https://assets.culturehq.com/single-story-widget-job-mappings_1732564233.js"; let cultureHqOrgId = "175"; let identifiers = ["data-req-id","data-category","data-sub-category","data-country"]; let
Company
Synopsys India
Location
Where?
Type
Full Time
Added
8 Apr 2026
Prep tools
Company
Synopsys India
Location
Where?
Type
Full Time
Added
8 Apr 2026
Req ID
93712504224