Static Timing Analysis (STA) / Timing Constraints & Closure Lead at AMD India

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AECG (Adaptive and Embedded Computing Group) Custom Design team at AMD Bangalore is at the forefront of developing high-performance, energy-efficient silicon solutions powering next-generation adaptive computing, AI, networking, and embedded platforms. The team is responsible for delivering world-class custom silicon and advanced SoC solutions across cutting-edge process technologies. As part of a highly collaborative global engineering organization, you will work alongside industry-leading architects, design engineers, physical design experts, and signoff teams to drive innovative products from concept to silicon. This role offers the opportunity to contribute to complex, high-frequency designs and play a critical role in enabling successful tape-outs for AMD's next-generation products. Key Responsibilities Develop and maintain complex multi-mode, multi-corner timing constraints (SDC) that are robust and consistent across RTL implementation and signoff environments. Ensure high-quality timing constraints using industry-standard validation tools such as Fishtail, GCA, and related methodologies. Define and validate timing signoff methodologies, modes, and corner requirements to achieve comprehensive timing coverage. Drive pre-route timing analysis, QoR optimization, and timing constraint cleanup to eliminate SDC-related issues and ensure high-quality handoff for STA signoff. Utilize strong expertise in SDC development, EDA timing analysis tools, and Tcl scripting within both EDA environments and standalone Linux-based scripting frameworks. Own timing closure activities for IPs, subsystems, and/or full-chip designs, ensuring timing convergence across all operating scenarios. Lead full-chip interface timing closure, including Design Rule Violation (DRV) analysis and closure. Generate and implement timing ECOs using tools such as DMSA, Tweaker, and related optimization utilities. Collaborate closely with Architecture, RTL Design, Physical Design, DFT, and Signoff teams to drive successful timing closure and tape-out readiness. Mentor junior engineers and contribute to the enhancement of timing methodologies, automation, and signoff practices. Preferred Qualifications & Experience Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related discipline. 8+ years of experience in timing constraint development and STA signoff for IP, subsystem, and full-chip designs in both flat and hierarchical implementation flows. Strong experience analyzing timing reports and identifying design, synthesis, implementation, and constraint-related timing issues. Hands-on experience with industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler, SpyGlass, Fishtail, Tweaker, and related timing signoff tools. Proven track record in timing closure of high-performance, high-frequency designs operating in the multi-GHz range. Experience driving full-chip STA closure, defining operational modes, corner strategies, and signoff requirements across multiple process-voltage-temperature (PVT) conditions. Strong understanding of DFT timing requirements and timing signoff across functional and test modes. Good understanding of physical design flows, ECO implementation methodologies, and backend timing optimization techniques. Deep knowledge of SDC constraint development and advanced timing analysis methodologies including OCV, AOCV, and POCV. Strong Tcl scripting and automation skills are mandatory. Excellent communication, problem-solving, and cross-functional collaboration skills with the ability to work effectively in a fast-paced global environment. Nice to Have Experience with automation and methodology development for STA and timing signoff flows. Experience supporting advanced technology nodes and complex SoC designs. Exposure to low-power design methodologies and timing signoff across multiple power domains. Education details : B.Tech / M.tech with 8+Yrs of exp #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. AECG (Adaptive and Embedded Computing Group) Custom Design team at AMD Bangalore is at the forefront of developing high-performance, energy-efficient silicon solutions powering next-generation adaptive computing, AI, networking, and embedded platforms. The team is responsible for delivering world-class custom silicon and advanced SoC solutions across cutting-edge process technologies. As part of a highly collaborative global engineering organization, you will work alongside industry-leading architects, design engineers, physical design experts, and signoff teams to drive innovative products from concept to silicon. This role offers the opportunity to contribute to complex, high-frequency designs and play a critical role in enabling successful tape-outs for AMD's next-generation products. Key Responsibilities Develop and maintain complex multi-mode, multi-corner timing constraints (SDC) that are robust and consistent across RTL implementation and signoff environments. Ensure high-quality timing constraints using industry-standard validation tools such as Fishtail, GCA, and related methodologies. Define and validate timing signoff methodologies, modes, and corner requirements to achieve comprehensive timing coverage. Drive pre-route timing analysis, QoR optimization, and timing constraint cleanup to eliminate SDC-related issues and ensure high-quality handoff for STA signoff. Utilize strong expertise in SDC development, EDA timing analysis tools, and Tcl scripting within both EDA environments and standalone Linux-based scripting frameworks. Own timing closure activities for IPs, subsystems, and/or full-chip designs, ensuring timing convergence across all operating scenarios. Lead full-chip interface timing closure, including Design Rule Violation (DRV) analysis and closure. Generate and implement timing ECOs using tools such as DMSA, Tweaker, and related optimization utilities. Collaborate closely with Architecture, RTL Design, Physical Design, DFT, and Signoff teams to drive successful timing closure and tape-out readiness. Mentor junior engineers and contribute to the enhancement of timing methodologies, automation, and signoff practices. Preferred Qualifications & Experience Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related discipline. 8+ years of experience in timing constraint development and STA signoff for IP, subsystem, and full-chip designs in both flat and hierarchical implementation flows. Strong experience analyzing timing reports and identifying design, synthesis, implementation, and constraint-related timing issues. Hands-on experience with industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler, SpyGlass, Fishtail, Tweaker, and related timing signoff tools. Proven track record in timing closure of high-performance, high-frequency designs operating in the multi-GHz range. Experience driving full-chip STA closure, defining operational modes, corner strategies, and signoff requirements across multiple process-voltage-temperature (PVT) conditions. Strong understanding of DFT timing requirements and timing signoff across functional and test modes. Good understanding of physical design flows, ECO implementation methodologies, and backend timing optimization techniques. Deep knowledge of SDC constraint development and advanced timing analysis methodologies including OCV, AOCV, and POCV. Strong Tcl scripting and automation skills are mandatory. Excellent communication, problem-solving, and cross-functional collaboration skills with the ability to work effectively in a fast-paced global environment. Nice to Have Experience with automation and methodology development for STA and timing signoff flows. Experience supporting advanced technology nodes and complex SoC designs. Exposure to low-power design methodologies and timing signoff across multiple power domains. Education details : B.Tech / M.tech with 8+Yrs of exp #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Static Timing Analysis (STA) / Timing Constraints & Closure Lead

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