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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Core Responsibilities 1. Strategy and Architecture Verification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure. Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers. Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing. 2. Execution and Technical Leadership Development: Write complex test cases and sequences to achieve high functional coverage. Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes. Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests. Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss. 3. Metric Management Coverage Analysis: Monitor and analyze functional and code coverage metrics. Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off: Define the "definition of done" and provide final technical approval for the verification phase. Soft Skills and Leadership Mentorship: Guiding junior engineers on coding standards and debugging techniques. Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams. Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines. Required Qualifications B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field 4–6 years of hands-on DV experience in semiconductor/ASIC/SoC companies We’re doing work that matters. Help us solve what others can’t.
Company
Cadence Design Systems
Location
BANGALORE
Type
Full Time
Experience
4–6 years
Posted
23 Jun 2026
Qualcomm India
Get a referral at Cadence Design Systems
Referrals beat cold applications ~5x — opens LinkedIn search.
Highest reply rate — they're paid to source
Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Lead Design Engineer role at Cadence Design Systems and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
Company
Cadence Design Systems
Location
BANGALORE
Type
Full Time
Experience
4–6 years
Posted
23 Jun 2026
Req ID
R54815
Cadence Design Systems
Qualcomm India
Semiconductor