Lead IP Verification engineer at AMD India

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Job Summary We are seeking an experienced and highly motivated Senior Engineer to lead a team responsible for verification of high-speed PHY IPs. The ideal candidate combines deep technical expertise in digital design verification with strong leadership skills to drive execution, mentor engineers, and deliver high-quality verification solutions for next-generation PHY technologies. This role requires close collaboration with Design, Architecture, AMS, Firmware, Physical Design, and Program Management teams to ensure first-pass silicon success. Key Responsibilities Technical Leadership Lead verification of complex high-speed PHY IPs such as DDR, LPDDR, PCIe, CXL, UCIe, Ethernet, USB, or SerDes. Own verification planning from architecture review through silicon bring-up support. Develop comprehensive verification strategies including: Test plans Functional coverage Assertion-based verification Constrained-random verification Formal verification where applicable Drive verification closure using coverage, bug convergence, and quality metrics. Review verification architecture, testbench design, and coding standards. Debug complex design and verification issues spanning digital, analog, and firmware interfaces. Team Leadership Lead and mentor a team of verification engineers. Plan project execution, priorities, and resource allocation. Conduct technical reviews and provide constructive feedback. Drive engineering excellence through best practices, reusable methodologies, and automation. Foster a collaborative, learning-oriented engineering culture. Coach engineers on career growth and technical development. Cross-Functional Collaboration Partner closely with Design Engineers AMS Engineers Firmware Engineers Physical Design Architecture Emulation/Validation Program Management to ensure alignment across all project phases. Participate in architecture reviews to improve verification readiness early in the development cycle. Methodology Development Drive adoption and continuous improvement of UVM methodology SystemVerilog Assertion-based verification Regression infrastructure Coverage-driven verification CI/CD verification flows AI-assisted verification productivity Verification automation frameworks Promote IP reuse and standardized verification environments across projects. Project Execution Estimate verification effort and schedules. Track milestones and execution risks. Drive timely issue resolution. Report project status using measurable quality metrics. Support silicon validation and customer issue debugging when required. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of ASIC/SoC verification experience. Experience leading technical teams or mentoring engineers. Strong expertise in: SystemVerilog UVM Assertions (SVA) Functional coverage Constrained-random verification Strong debugging skills. Experience with scripting languages such as Python, Perl, or Tcl. Experience with industry-standard simulators and regression environments. Preferred Experience Experience verifying one or more of: DDR5/LPDDR5/LPDDR6 PHY UCIe PHY PCIe Gen5/Gen6 Ethernet PHY USB4 Display PHY SerDes #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Job Summary We are seeking an experienced and highly motivated Senior Engineer to lead a team responsible for verification of high-speed PHY IPs. The ideal candidate combines deep technical expertise in digital design verification with strong leadership skills to drive execution, mentor engineers, and deliver high-quality verification solutions for next-generation PHY technologies. This role requires close collaboration with Design, Architecture, AMS, Firmware, Physical Design, and Program Management teams to ensure first-pass silicon success. Key Responsibilities Technical Leadership Lead verification of complex high-speed PHY IPs such as DDR, LPDDR, PCIe, CXL, UCIe, Ethernet, USB, or SerDes. Own verification planning from architecture review through silicon bring-up support. Develop comprehensive verification strategies including: Test plans Functional coverage Assertion-based verification Constrained-random verification Formal verification where applicable Drive verification closure using coverage, bug convergence, and quality metrics. Review verification architecture, testbench design, and coding standards. Debug complex design and verification issues spanning digital, analog, and firmware interfaces. Team Leadership Lead and mentor a team of verification engineers. Plan project execution, priorities, and resource allocation. Conduct technical reviews and provide constructive feedback. Drive engineering excellence through best practices, reusable methodologies, and automation. Foster a collaborative, learning-oriented engineering culture. Coach engineers on career growth and technical development. Cross-Functional Collaboration Partner closely with Design Engineers AMS Engineers Firmware Engineers Physical Design Architecture Emulation/Validation Program Management to ensure alignment across all project phases. Participate in architecture reviews to improve verification readiness early in the development cycle. Methodology Development Drive adoption and continuous improvement of UVM methodology SystemVerilog Assertion-based verification Regression infrastructure Coverage-driven verification CI/CD verification flows AI-assisted verification productivity Verification automation frameworks Promote IP reuse and standardized verification environments across projects. Project Execution Estimate verification effort and schedules. Track milestones and execution risks. Drive timely issue resolution. Report project status using measurable quality metrics. Support silicon validation and customer issue debugging when required. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of ASIC/SoC verification experience. Experience leading technical teams or mentoring engineers. Strong expertise in: SystemVerilog UVM Assertions (SVA) Functional coverage Constrained-random verification Strong debugging skills. Experience with scripting languages such as Python, Perl, or Tcl. Experience with industry-standard simulators and regression environments. Preferred Experience Experience verifying one or more of: DDR5/LPDDR5/LPDDR6 PHY UCIe PHY PCIe Gen5/Gen6 Ethernet PHY USB4 Display PHY SerDes #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Lead IP Verification engineer

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