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Get a referral at Intel India
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Hi {{their name}}, I'm I. I just applied for the Senior Physical Design Engineer STA role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
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- Perform timing analysis and optimization to meet design specifications at the Partition and IP level levels. - Generate and verify timing constraints, addressing timing violations across complex SoC designs. - Conduct timing rollups, ensuring designs meet functionality, performance, and power goals. - Develop performance and power-optimized clock networks, collaborating with clocking and backend teams. - Define methodologies for high-quality timing models to optimize physical design team efficiency. - Establish process, voltage, and temperature (PVT) conditions for timing analysis based on product requirements. - Work closely with architecture, clocking design, and logic design teams to support flow development, chip integration, and clock network validation. - Drive timing fixes, clocking balance, and power delivery through close coordination with full-chip designers. - Ensure timing budgets are met and collaborate on timing closure reviews.
Company
Intel India
Location
India, Bangalore
Type
Full Time
Posted
12 Jun 2026
Get a referral at Intel India
Referrals beat cold applications ~5x — opens LinkedIn search.
Highest reply rate — they're paid to source
Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Senior Physical Design Engineer STA role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
Company
Intel India
Location
India, Bangalore
Type
Full Time
Posted
12 Jun 2026
Req ID
JR0283963
Minimum
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field. - 4+ years of experience with a Bachelor's degree or 3+ years of experience with a Master's degree in timing analysis and optimization for SoC designs. - Proficiency in static timing analysis, timing budgeting, timing constraint adaptation, and clock network optimization. - Expertise in methodologies relating to timing models, PVT conditions, and timing rollups. Preferred
Qualcomm India