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Get a referral at Intel India
Referrals beat cold applications ~5x — opens LinkedIn search.
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Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Static Timing Analysis Engineer role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
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- Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels. - Generate and verify timing constraints, addressing and resolving timing violations during SoC development. - Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines. - Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process. - Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions. - Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance, power delivery optimization, and efficient partitioning. - Partner closely with the clocking team to refine methodologies and validate integration flows for chip-level timing solutions.
Company
Intel India
Location
India, Bangalore
Type
Full Time
Posted
22 May 2026
Get a referral at Intel India
Referrals beat cold applications ~5x — opens LinkedIn search.
Highest reply rate — they're paid to source
Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Static Timing Analysis Engineer role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
Company
Intel India
Location
India, Bangalore
Type
Full Time
Posted
22 May 2026
Req ID
JR0284206
Minimum
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years with a Master's degree, or 4+ years with a PhD. - Proficiency in static timing analysis tools and methodologies. - Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques. - Technical understanding of PVT conditions and their application in timing analysis. Preferred