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Get a referral at Intel India
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Hi {{their name}}, I'm I. I just applied for the Senior Design Verification Engineer role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
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- Own verification planning and execution for assigned IP blocks and features at IP and subsystem level; drive test plans through coverage closure with direct accountability for quality. - Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of the verification collateral you deliver. - Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed to unblock progress, - Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication, own debug for your blocks end-to-end. - Drive functional coverage planning and coverage closure for assigned blocks; contribute to quality signoff with increasing independence. - Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency. - Begin mentoring junior engineers on verification practices, debugging techniques, and code quality.
Company
Intel India
Location
India, Bangalore
Type
Full Time
Experience
8–12 years
Posted
9 Apr 2026
Get a referral at Intel India
Referrals beat cold applications ~5x — opens LinkedIn search.
Highest reply rate — they're paid to source
Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Senior Design Verification Engineer role at Intel India and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
Company
Intel India
Location
India, Bangalore
Type
Full Time
Experience
8–12 years
Posted
9 Apr 2026
Req ID
JR0282830
Intel India
Minimum
- BS/MS in Electrical Engineering, Computer Science, or related field, with 8-12 years of relevant experience in design verification; solid background in IP-level DV with meaningful exposure to subsystem-level verification. - Strong and growing expertise in interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; working understanding of cache coherency and memory consistency models. - Strong background in simulation-based verification methodologies including UVM, SVA, and ABV; hands-on testbench development, debugging, and coverage-driven verification. - Hands-on coding proficiency across SystemVerilog/UVM, C/C++, and Python; track record of delivering clean, reusable, and maintainable verification code and automation scripts. - Comfort using AI-assisted development tools as part of everyday workflow for coding, debugging, and test development. - Ability to collaborate effectively across architecture, design, and software teams; enough context outside core DV to contribute meaningfully when needed. Preferred
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