Senior Verification Engineer - HSIO Unit Level at NVIDIA India

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are seeking hardworking, determined, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's unit level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips. What you'll be doing: You will develop UVM-based verification test benches and methodologies. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC. During the course of a project, you will drive the following aspects of verification for your unit: Architect the testbenches and craft verification environment using SV and UVM methodology Define test plans, tests and verification infrastructure for modules, clusters and systems Build efficient and reusable bus functional models, monitors, checkers, and scoreboards Implement functional coverage and coordinate the verification closure process for the unit Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust What we need to see: BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification. Proven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch Experience in the latest verification methodologies like SV and UVM Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization Ways to stand out from the crowd: Exposure on using AI (Claude and Curser) extensively for code development would be a big plus A mentality towards constant improvement and looking to build a multiplier effect through your work and automation Exposure to Formal verification would be excellent We have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting the newest technology, we want to hear from you. Join us and be part of something outstanding! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ #LI-Hybrid

Senior Verification Engineer - HSIO Unit Level

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