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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities Design Verification for interconnect IP Relevant experience in interconnect and subsystems is strongly preferred Crafting verification plans and executing on those plans to verify highly complex and configurable designs. Responsible for coverage collection and closure Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope Required Skills and Experience: 8+ years of design verification experience BS (or higher) in EE/Computer Engineering Strong technical and interpersonal skills Excellent knowledge of Interconnects, NoCs and design verification fundamentals. Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches Experience with development of fully automated flows Exposure to scripting languages like Perl, Unix shell or similar languages Experience with Formal Verification will be a plus Experience with Gate Level Simulations Excellent written and oral communication skills necessary We’re doing work that matters. Help us solve what others can’t.
Company
Cadence Design Systems
Location
BANGALORE
Type
Full Time
Posted
12 Mar 2025
Get a referral at Cadence Design Systems
Referrals beat cold applications ~5x — opens LinkedIn search.
Highest reply rate — they're paid to source
Engineers on the team can refer you internally
People who posted "we're hiring" recently
Hi {{their name}}, I'm I. I just applied for the Principal Design Engineer role at Cadence Design Systems and your profile stood out — would love a quick referral or even just a chat about the team. Happy to share my resume. Thanks!
Company
Cadence Design Systems
Location
BANGALORE
Type
Full Time
Posted
12 Mar 2025
Req ID
R45706
Qualcomm India
Qualcomm India
Qualcomm India