ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years

Qualifications

* Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience. * Knowledge of the latest innovative trends in DFT, test and silicon engineering. * Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. * Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime * Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design * Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. * Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime * Experience working with Gate level simulation, debugging with VCS and other simulators. * Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 * Strong verbal skills and ability to thrive in a multifaceted environment * Scripting skills: Tcl, Python/Perl. Preferred

Qualifications

• * Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification * DFT CAD development - Test Architecture, Methodology and Infrastructure * Test Static Timing Analysis * Post silicon validation using DFT patterns.
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