Sr Engineer, Die Design Engineering APTD

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Advanced Packaging Technology Development org is seeking an experienced and technically strong Die Design & Layout Senior Engineer to support High Bandwidth Memory (HBM) packaging program. This role sits at the critical intersection of silicon design and advanced packaging, responsible for executing die-level design strategy that enables world-class HBM product integration. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. Key Responsibilities TSV & 3D Integration ∙ Define TSV placement strategy considering keep-out zones, stress-aware layout, CMP density, and wafer thinning constraints ∙ Oversee micro-bump array design, landing pad rules, and RDL routing in coordination with packaging engineering ∙ Ensure die design supports reliable thermo-compression bonding (TCB) and underfill processes through DFM-aware layout decisions ∙ Collaborate with process integration teams on TSV reveal, backside RDL, and hybrid bonding design requirements as technology evolves Multi-Functional Collaboration ∙ Serve as the primary technical interface between die design team and packaging, process integration, test, reliability, and product engineering teams ∙ Work closely with failure analysis teams to support root cause investigation of layout-related yield or reliability excursions Technology Roadmap & Innovation ∙ Stay current with evolving HBM standards (JEDEC HBM3, HBM3E, and beyond) and translate new requirements into die design methodology updates ∙ Evaluate and adopt new EDA tools, design methodologies, and layout automation techniques to improve team efficiency and design quality ∙ Contribute to advanced packaging technology roadmap discussions including hybrid bonding, chiplet integration, and next-generation interconnect scaling ∙ Drive IP reuse, layout template standardization, and design kit development to accelerate future program execution Required Qualifications Education ∙ Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required Experience ∙ 5+ years of experience in die design and physical layout engineering ∙ Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent) ∙ Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL Technical Skills ∙ Deep expertise in physical design and layout using industry-standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler) ∙ Strong knowledge of DRC/LVS/ERC sign-off flows and foundry PDK rule interpretation ∙ Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints ∙ Working knowledge of DFT structures relevant to advanced packaging: daisy chains, BIST, boundary scan, IEEE P1838 ∙ Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E) ∙ Understanding of power integrity, signal integrity, and thermal considerations at the die-package interface ∙ Experience with parasitic extraction and layout-driven optimization for high-speed memory interfaces Preferred Qualifications ∙ Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints ∙ Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration ∙ Knowledge of HBM assembly (TCB, underfill, wafer thinning) ∙ Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management ∙ Exposure to reliability physics relevant to advanced packaging: electromigration, stress voiding, thermo-mechanical degradation ∙ Published work or patents in advanced packaging, 3D-IC design, or memory interface design About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. 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